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| DRAM MODULE KMM5328004CSW/CSWG 4Byte 8Mx32 SIMM (4Mx16 base) Revision 0.0 June 1999 DRAM MODULE Revision History Version 0.0 (June 1999) * The 4th. generation of 64Mb DRAM components are applied for this module. KMM5328004CSW/CSWG DRAM MODULE KMM5328004CSW/CSWG EDO Mode 8M x 32 DRAM SIMM Using 4Mx16, 4K Refresh, 5V GENERAL DESCRIPTION The Samsung KMM5328004C is a 8Mx32bits Dynamic RAM high density memory module. The Samsung KMM5328004C consists of four CMOS 4Mx16bits DRAMs in TSOP packages mounted on a 72-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The KMM5328004C is a Single In-line Memory Module with edge connections and is intended for mounting into 72 pin edge connector sockets. KMM5328004CSW/CSWG FEATURES * Part Identification - KMM5328004CSW(4K cycles/64ms Ref, TSOP, Solder) - KMM5328004CSWG(4K cycles/64ms Ref, TSOP, Gold) * Extended Data Out Mode Operation * CAS-before-RAS & Hidden Refresh capability * RAS-only refresh capability * TTL compatible inputs and outputs * Single +5V10% power supply * JEDEC standard PDpin & pinout * PCB : Height(1000mil), double sided component PERFORMANCE RANGE Speed -5 -6 tRAC 50ns 60ns tCAC 13ns 15ns tRC 84ns 104ns tHPC 20ns 25ns PIN CONFIGURATIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 Vcc NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 A11 Vcc A8 A9 RAS3 RAS2 NC NC Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Symbol NC NC Vss CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 Vcc DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC Vss PIN NAMES Pin Name A0 - A11 DQ0-7, DQ9-16 DQ18-25, DQ27-34 W RAS0 - RAS3 CAS0 - CAS3 PD1 -PD4 Vcc Vss NC Function Address Inputs Data In/Out Read/Write Enable Row Address Strobe Column Address Strobe Presence Detect Power(+5V) Ground No Connection PRESENCE DETECT PINS (Optional) Pin PD1 PD2 PD3 PD4 50NS NC Vss Vss Vss 60NS NC Vss NC NC SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. DRAM MODULE FUNCTIONAL BLOCK DIAGRAM KMM5328004CSW/CSWG DQ0 - DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U0 RAS0/RAS2 47 CAS0 47 CAS1 RAS LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ9 - DQ16 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 U3 RAS RAS1/RAS3 LCAS UCAS DQ8 DQ9 DQ10 DQ11 OE DQ12 DQ13 DQ14 W A0-A11 DQ15 UCAS OE W A0-A11 DQ18 - DQ25 RAS 47 CAS2 47 CAS3 UCAS LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 U2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ27 - DQ34 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 U5 RAS LCAS DQ8 DQ9 DQ10 DQ11 OE DQ12 DQ13 DQ14 W A0-A11 DQ15 UCAS OE W A0-A11 W A0-A11 Vcc 0.1 or 0.22uF Capacitor for each DRAM Vss To all DRAMs DRAM MODULE ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg Pd IOS KMM5328004CSW/CSWG Rating -1 to +7.0 -1 to +7.0 -55 to +125 4 50 Unit V V C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70C) Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.4 -1.0*2 Typ 5.0 0 Max 5.5 0 VCC*1 0.8 Unit V V V V *1 : VCC+2.0V at pulse width20ns, which is measured at VCC. *2 : -2.0V at pulse width20ns, which is measured at VSS. DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL Speed -5 -6 Dont care -5 -6 -5 -6 Dont care -5 -6 Dont care Dont care KMM5328004CSW/CSWG Min - Max 244 224 8 244 224 224 204 4 244 224 10 10 0.4 Unit mA mA mA mA mA mA mA mA mA mA uA uA V V -10 -10 2.4 - ICC1 : Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3 : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4 :Hyper Page Mode Current * (RAS=VIL, CAS cycling : tHPC=min) ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V) ICC6 : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) I(IL) : Input Leakage Current (Any input 0VINVcc+0.5V, all other pins not under test=0 V) I(OL) : Output Leakage Current(Data Out is disabled, 0VVOUTVcc) VOH : Output High Voltage Level (IOH = -5mA) VOL : Output Low Voltage Level (IOL = 4.2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one EDO mode cycle time, tHPC. DRAM MODULE CAPACITANCE (TA = 25C, VCC=5V, f = 1MHz) Item Input capacitance[A0-A11] Input capacitance[W] Input capacitance[RAS0/RAS2, RAS1/RAS3] Input capacitance[CAS0 - CAS3] Input/Output capacitance[DQ0-7, 9-16,18-25, 27-34] Symbol CIN1 CIN2 CIN3 CIN4 CDQ KMM5328004CSW/CSWG Min - Max 30 38 24 24 24 Unit pF pF pF pF pF AC CHARACTERISTICS (0CTA70C, Vcc=5.0V10%. See notes 1,2.) Test condition : Vih/Vil=2.6/0.8V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter Random read or write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay from CAS Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referenced to CAS Read command hold referenced to RAS Write command set-up time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Refresh period CAS setup time (CAS-before-RAS refresh) CAS hold time (CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Symbol -5 Min 84 50 13 25 3 3 1 30 50 13 38 8 20 15 5 0 10 0 8 25 0 0 0 0 10 10 13 8 0 8 64 5 10 5 28 5 10 5 35 10K 37 25 10K 13 50 3 3 1 40 60 15 45 10 20 15 5 0 10 0 10 30 0 0 0 0 10 10 15 10 0 10 64 10K 45 30 10K 13 50 Max Min 104 60 15 30 -6 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns 3 9 9 8 8 7 4 9 3,4,10 3,4,5 3,10 3 6,12 2 Note tRC tRAC tCAC tAA tCLZ tCEZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCS tWCH tWP tRWL tCWL tDS tDH tREF tCSR tCHR tRPC tCPA DRAM MODULE Test condition : Vih/Vil=2.6/0.8V, Voh/Vol=2.0/0.8V, output loading CL=100pF Parameter Hyper page mode cycle time CAS precharge time (Hyper page cycle) RAS pulse width (Hyper page cycle) RAS hold time from CAS precharge W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay W pulse width Symbol -5 Min 20 8 50 30 10 10 5 3 3 15 5 13 13 200K Max KMM5328004CSW/CSWG AC CHARACTERISTICS (0CTA70C, Vcc=5.0V10%. See notes 1,2.) -6 Min 25 10 60 35 10 10 5 3 3 15 5 15 15 200K Max Unit ns ns ns ns ns ns ns ns ns ns ns 6,12 6 Note 11 tHPC tCP tRASP tRHCP tWRP tWRH tDOH tREZ tWEZ tWED tWPE NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit and is not referenced for VOH or VOL. 7. tWCS is non-restrictive operating parameter. It is included in the data sheet as electrical characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit access time is controlled by tAA. 11. tASC6ns, Assume tT=2.0ns. 12. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going , the open circuit condition of the output is achieved by RAS going. DRAM MODULE READ CYCLE KMM5328004CSW/CSWG tRC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tWEZ tAA OE VIH VIL - tCEZ tOEZ tOEA DQ VOH VOL - tRAC OPEN tOLZ tCAC tCLZ tREZ DATA-OUT Dont care Undefined DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM5328004CSW/CSWG tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRAD tRSH tCAS tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL tWCS W VIH VIL - tWCH tWP OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN KMM5328004CSW/CSWG tRC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tRAD tRAL tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL W VIH VIL - tWP OE VIH VIL - tOED tDS tOEH tDH DATA-IN DQ VIH VIL - Dont care Undefined DRAM MODULE READ - MODIFY - WRITE CYCLE KMM5328004CSW/CSWG tRAS RAS VIH VIL - tRWC tRP tCRP CAS VIH VIL - tRCD tRAD tRAH tRSH tCAS tASR VIH VIL - tASC tCAH tCSH A ROW ADDR COLUMN ADDRESS tAWD tCWD W VIH VIL - tRWL tCWL tWP tRWD OE VIH VIL - tOEA tOLZ tCLZ tCAC tAA tRAC VALID DATA-OUT tOED tOEZ tDS tDH VALID DATA-IN DQ VI/OH VI/OL - Dont care Undefined DRAM MODULE HYPER PAGE READ CYCLE KMM5328004CSW/CSWG tRASP RAS VIH VIL o tRP tCSH tCRP CAS VIH VIL - tRHCP tHPC tCP tHPC tCAS tCP tHPC tCAS tCP tCAS tRCD tCAS tRAD tASR A VIH VIL - tRAH tASC tCAH tASC tCAH tASC tCAH COLUMN ADDR tASC tCAH tREZ ROW ADDR COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tRRH tRCS W VIH VIL - tRCH tCPA tCAC tAA tCPA tCAC tOEA tCAC tAA tCPA tOCH tOEA tOEP tDOH VALID DATA-OUT tCAC tAA tCHO tOEP tAA OE VIH VIL - tCAC tRAC DQ VOH VOL - tOEA tOEZ VALID DATA-OUT VALID DATA-OUT tOEZ tOEZ tOLZ tCLZ VALID DATA-OUT Dont care Undefined DRAM MODULE HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM5328004CSW/CSWG tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tHPC tRCD tCAS tRAD tCSH tASC tCP tCAS o tHPC tCP tRSH tCAS tASR A VIH VIL - tRAH tCAH tASC tCAH o o tASC tCAH ROW ADDR. COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tWCS W VIH VIL - tWCH tWCS tWCH tWP tCWL o o o tWCS tWCH tWP tCWL tRWL tWP tCWL OE VIH VIL - tDS DQ VIH VIL - tDH VALID DATA-IN tDS tDH o VALID DATA-IN tDS tDH o VALID DATA-IN Dont care Undefined DRAM MODULE HYPER PAGE READ-MODIFY-WRITE CYCLE KMM5328004CSW/CSWG RAS VIH VIL - tRASP tCSH tCRP tRSH tHPRWC tRCD tCAS tRAD tRAH tASR tASC COL. ADDR tRP tCP tCAS tRAL tCRP CAS VIH VIL - tCAH tASC COL. ADDR tCAH A VIH VIL - ROW ADDR tRCS W VIH VIL - tCWL tWP tCWD tAWD tCPWD tOEA tOED tRWL tCWL tWP tCWD tAWD tRWD tOEA tCAC tAA tRAC tOEZ tDS tCAC OE VIH VIL - tOED tDH tAA tDH tOEZ tDS DQ VI/OH VI/OL - tCLZ tOLZ VALID DATA-OUT tCLZ VALID DATA-IN tOLZ VALID DATA-OUT VALID DATA-IN Dont care Undefined DRAM MODULE HYPER PAGE READ AND WRITE MIXED CYCLE KMM5328004CSW/CSWG tRASP RAS VIH VIL READ(tCAC) READ(tCPA) WRITE READ(tAA) tRP tHPC tCP CAS VIH VIL - tHPC tCP tCP tCAS tASC COL. ADDR tHPC tCAS tASC tCAH COL. ADDR tRAD tASR tRAH tASC tCAS tCAH tCAS tCAH tCAH tASC COLUMN ADDRESS A VIH VIL - ROW ADDR COLUMN ADDRESS tRCS W VIH VIL - tRCH tRCS tRCH tWCS tWCH tRCH tWPE tCLZ tCPA OE VIH VIL - tWED DQ VI/OH VI/OL - tOEA tCAC tAA tRAC tWEZ tDH tWEZ VALID DATA-OUT tDS VALID DATA-IN tAA VALID DATA-OUT tREZ VALID DATA-OUT Dont care Undefined DRAM MODULE RAS - ONLY REFRESH CYCLE* NOTE : W, OE, DIN = Dont care DOUT = OPEN tRC RAS VIH VIL - KMM5328004CSW/CSWG tRP tRAS tCRP tRPC tCRP CAS VIH VIL - tASR A VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Dont care tRP RAS VIH VIL - tRC tRAS tRP tRPC tCP tCSR tCHR tRPC CAS VIH VIL - tWRP W VIH VIL - tWRH tCEZ DQ VOH VOL - OPEN Dont care Undefined * In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off. DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) KMM5328004CSW/CSWG tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP CAS VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRRH tWRH tWRP tAA OE VIH VIL - tOEA tOLZ tCAC tCLZ tRAC tOEZ DATA-OUT tCEZ tREZ tWEZ DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN KMM5328004CSW/CSWG tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP tRCD tRSH tCHR CAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWCS W VIH VIL - tWRP tWCH tWP tWRH OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE KMM5328004CSW/CSWG tRP RAS VIH VIL VIH VIL - tRAS tCPT tCHR tRSH tCAS tRAL tASC tCAH tCSR CAS A VIH VIL - COLUMN ADDRESS READ CYCLE W OE VIH VIL VIH VIL - tWRP tWRH tAA tRCS tCAC tRRH tRCH DQ VOH VOL - tCLZ tOEA tOEZ DATA-OUT tCEZ tREZ tWEZ WRITE CYCLE W VIH VIL VIH VIL - tWRP tWRH tWCS tRWL tCWL tWCH tWP OE tDS DQ VIH VIL - tDH DATA-IN READ-MODIFY-WRITE tWRP W VIH VIL - tWRH tRCS tAWD tCWD tCAC tWP tCWL tRWL tAA tOEA OE VIH VIL - tOED tCLZ tOEZ tDS tDH DQ VI/OH VI/OL VALID DATA-OUT VALID DATA-IN Dont care Undefined NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules. DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Dont care KMM5328004CSW/CSWG tRP RAS VIH VIL - tRASS tRPS tRPC tCP tCSR tCHS tRPC CAS VIH VIL - tCEZ DQ VOH VOL - OPEN W VIH VIL - tWRP tWRH TEST MODE IN CYCLE NOTE : OE , A = Dont care tRC tRAS tRPC tCP CAS VIH VIL - tRP RAS VIH VIL - tRP tRPC tCSR tCHR tWTS W VIH VIL - tWTH tCEZ DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE PACKAGE DIMENSIONS KMM5328004CSW/CSWG Units : Inches (millimeters) 4.250(107.95) 3.984(101.19) .133(3.38) R.062(1.57) .125 DIA.002(3.18.051) .400(10.16) 1.000(25.40) .250(6.35) R.062.004(R1.57.10) .080(2.03) .250(6.35) .250(6.35) 3.750(95.25) ( Front view ) ( Back view ) Gold/Solder Plating Lead 0.150MAX (3.81MAX) .010(.25)MAX 0.125MIN (3.20MIN) .054(1.37) .047(1.19) .050(1.27) .041.004(1.04.10) Tolerances : .005(.13) unless otherwise specified NOTE : The used device is 4Mx16 DRAM, TSOPII DRAM Part No. : KMM5328004CSW/CSWG -- KM416C4104CS (400 mil) |
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